1. Field of the Invention
The present invention is related to a device for addressing a memory designed for digital computers. The addressing device in question may be, for example, applied to Read Only Memories (hereinafter referred to as ROM) of the Semi Conductor MOS type or to read/write memories (hereinafter referred to as RAM) of the static type.
To be more precise, said device comprises a plurality of memories with a predefined access time designed to store a plurality of data words. Furthermore the storage elements are successively addressed by a plurality of address, each of which having a first part in common and a second part which is variable; a plurality of read registers connected to storage units for writing the relative read words, the reading registers having a reading time that is considerably briefer than the access time of the memory elements and of a data output channel connected to the read registers.
2. Description of the Prior Art
There are known storage address devices, in which the first part of the address is used to select a word common to all elements (hereinafter referred to as "chip") constituting the memory. The second part of the address is decoded and provides an enabling signal containing the specific address of the chip. The reading of different words from memory results therefore in successive reading cycles.
Each read cycle includes a fixed access time and a time during which output data are valid. The major inconvenience of such a device is due to the fact that a memory access time is required for any addressing sequence. To be more precise, the length of the read cycle remains unaltered during memory access time for consecutive addressing, and this time cannot be reduced.